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general description the MAX17552 high-efficiency, high-voltage, syn - chronous step-down dc-dc converter with integrated mosfets operates over a 4v to 60v input voltage range. the converter can deliver output current up to 100ma at output voltages of 0.8v to 0.9 x v in . the output voltage is accurate to within 1.75% over the -40c to +125c temperature range. the device employs a peak-current-mode control architecture with a mode pin that can be used to operate the device in pulse-width modulation (pwm) or pulse- frequency modulation (pfm) control schemes. pwm operation provides constant frequency operation at all loads and is useful in applications sensitive to variable switching frequency. pfm operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. the converter consumes only 22a of no-load supply current in pfm mode. the low- resistance, on-chip mosfets ensure high efficiency at full load and simplify pcb layout. the device offers programmable switching frequency to optimize solution size and efficiency. programmable soft-start allows the user to reduce the inrush currents. an en/uvlo pin allows the user to turn on/off the device at the desired input-voltage level. an open-drain reset pin allows output-voltage monitoring. the device operates over the -40c to +125c industrial temperature range and is available in a compact 10-pin (3mm x 2mm) tdfn and 10-pin (3mm x 3mm) max ? packages. simulation models are available. applications industrial sensors and process control 4maC20ma current-loop powered sensors high-voltage ldo replacement battery-powered equipment hvac and building control general-purpose point-of-load benefts and features eliminates external components and reduces total cost ? no schottkysynchronous operation for high efficiency and reduced cost ? internal compensation ? fixed internal 5.1ms or programmable soft-start ? all-ceramic capacitors, ultra-compact layout reduces number of dc-dc regulators to stock ? wide 4v to 60v input voltage range ? adjustable 0.8v to 0.9 x v in output voltages ? delivers up to 100ma load current ? 100khz to 2.2mhz adjustable switching frequency range with external synchronization ? configurable between pfm and forced-pwm modes reduces power dissipation ? 22a no load supply current ? peak efficiency > 90% ? pfm feature for high light-load efficiency ? 1.2a (typ) shutdown current operates reliably in adverse industrial environments ? peak current-limit protection ? built-in output-voltage monitoring with open-drain reset pin ? programmable en/uvlo threshold ? monotonic startup into prebiased output ? overtemperature protection ? -40c to +125c industrial/automotive temperature range ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX17552.related . max is a registered trademark of maxim integrated products, inc. 19-6903; rev 1; 6/14 evaluation kit available MAX17552 60v, 100ma, ultra-small, high-efficiency, synchronous step-down dc-dc converter with 22a no-load supply current
in, en/uvlo, v out , reset to gnd ..................... -0.3v to 70v lx to gnd ...................................................... -0.3v to in + 0.3v rt/sync, ss, fb, mode to gnd ........................... -0.3v to 6v lx total rms current ........................................................ 1.6a output short-circuit duration .................................... continuous operating temperature range ......................... -40c to +125c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c tdfn continuous power dissipation (t a = +70c) (derate 14.9mw/c above +70c) ..................... 1188.7mw junction-to-ambient thermal resistance ( ja ) ....... 67.3c/w junction-to-case thermal resistance ( jc ) ............ 18.2c/w max continuous power dissipation (t a = +70c) (derate 8.8mw/c above +70c) .......................... 707.3mw junction-to-ambient thermal resistance ( ja ) ..... 113.1c/w junction-to-case thermal resistance ( jc ) ............... 42c/w (note 1) (v in = 24v, v gnd = 0v, v vout = 3.3v, v fb = 0.85v, v en/uvlo = 1.5v, rt/sync = 191k, lx = ss = mode = reset = uncon - nected; t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to gnd, unless otherwise noted) (note 2) parameter symbol conditions min typ max units input supply (in) input voltage range v in 4 60 v input shutdown current i in-sh v en/uvlo = 0v, t a = +25c 0.67 1.2 2.25 a input supply current i q-pfm v mode = unconnected (note 2) 18 32 i q-pwm normal switching mode, v in = 24v 245 525 760 external bias (v out) v out switchover threshold 2.96 3.05 3.12 v enable/uvlo (en/uvlo) en/uvlo threshold v enr v en/uvlo rising 1.2 1.25 1.3 v v enf v en/uvlo falling 1.1 1.15 1.2 v en-truesd v en/uvlo falling, true shutdown 0.7 en/uvlo leakage current i en v en/uvlo = 1.3v, t a = +25c -100 +100 na power mosfets high-side pmos on-resistance r ds-onh i lx = 0.1a (sourcing) 1.5 2.7 5.1 low-side nmos on-resistance r ds-onl i lx = 0.1a (sinking) 0.8 1.4 2.6 lx leakage current i lx-lkg v en = 0v, t a = +25c, v lx = (v gnd + 1v) to (v in - 1v) -1 +1 a maxim integrated 2 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics electrical characteristics MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
(v in = 24v, v gnd = 0v, v vout = 3.3v, v fb = 0.85v, v en/uvlo = 1.5v, rt/sync = 191k, lx = ss = mode = reset = uncon - nected; t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to gnd, unless otherwise noted) (note 2) parameter symbol conditions min typ max units soft-start (ss) soft-start time t ss ss = unconnected 4.4 5.1 5.8 ms ss charging current i ss 4.7 5 5.3 a feedback (fb) fb regulation voltage v fb-reg mode = gnd 0.786 0.8 0.814 v mode = unconnected 0.786 0.812 0.826 fb input leakage current i fb v fb = 1v, t a = 25c -100 +100 na current limit peak current-limit threshold i peak-limit 185 210 235 ma negative current-limit threshold i sink-limit v mode = gnd 79 105 130 ma v mode = unconnected 0.01 pfm current level i pfm v mode = unconnected 50 72 90 ma oscillator (rt/sync) switching frequency f sw r rt = 422k 90 100 111 khz r rt = 191k 205 220 235 r rt = 130k 295 319 340 r rt = 69.8k 540 592 638 r rt = 45.3k 813 900 973 r rt = 19.1k 1.86 2.08 2.3 mhz switching frequency adjustable range see the switching frequency (rt/ sync) section for details 100 2200 khz sync input frequency 1.1 x f sw 2200 khz sync pulse minimum off-time 40 ns sync rising threshold v sync-h 1 1.22 1.44 v hysteresis v sync-hys 0.115 0.18 0.265 no of sync pulses to enable synchronization 1 cycles timing minimum on-time t on-min 46 82 128 ns maximum duty cycle d max f sw 600khz, v fb = 0.98 x v fb-reg 90 94 98 % f sw > 600khz, v fb = 0.98 x v fb-reg 87 92 maxim integrated 3 electrical characteristics (continued) MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
(v in = 24v, v gnd = 0v, v vout = 3.3v, v fb = 0.85v, v en/uvlo = 1.5v, rt/sync = 191k, lx = ss = mode = reset = uncon - nected; t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c. all voltages are referenced to gnd, unless otherwise noted) (note 2) note 2: actual i q-pfm in the application circuit is higher due to additional current in the output voltage feedback resistor divider. for example, i q-pfm (mode = unconnected) = 26a for figure 6, 22a for figure 7, and 78a for figure 11. note 3: all limits are 100% tested at +25c. limits over temperature are guaranteed by design. parameter symbol conditions min typ max units reset fb threshold for reset rising v fb-okr v fb rising 93 95 97 % fb threshold for reset falling v fb-okf v fb falling 90 92 94 % reset delay after fb reaches 95% regulation 2.1 ms reset output level low i reset = 1ma 0.23 v reset output leakage current v fb = 1.01 x v fb-reg , t a = +25c 1 a mode mode pfm threshold v mode-pfm 1 1.22 1.44 v mode hysteresis v mode-hys 0.19 v mode internal pullup resistor v mode = unconnected 235 k v mode = gnd 1390 thermal shutdown thermal-shutdown threshold temperature rising 160 c thermal-shutdown hysteresis 20 c maxim integrated 4 electrical characteristics (continued) MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
(v in = 24v, v gnd = 0v, v out = 3.3v, v en/uvlo = 1.5v, rt/sync = 191k, c in = 1f, t a = +25c unless otherwise noted) 0 10 20 30 40 50 60 70 80 90 100 1 10 100 efficiency (%) load current (ma) efficiency vs. load current toc1 v in = 24v v in = 36v v in = 12v figure 6 application circuit, pfm mode v out = 5v 0 10 20 30 40 50 60 70 80 90 100 1 10 100 efficiency (%) load current (ma) efficiency vs. load current toc2 v in = 36v v in = 12v v in = 24v figure 7 application circuit, pfm mode v out = 3.3v 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 efficiency (%) load current (ma) efficiency vs. load current toc3 v in = 48v v in = 36v v in = 24v v in = 12v v in = 60v figure 6 application circuit, pwm mode v out = 5v 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 efficiency (%) load current (ma) efficiency vs. load current toc4 v in = 36v v in = 60v v in = 12v v in = 24v figure 7 application circuit pwm mode, v out = 3.3v v in = 6v v in = 48v 4.96 4.99 5.02 5.05 5.08 0 20 40 60 80 100 output voltage (v) load current (ma) output voltage vs. load current toc5 figure 6 application circuit, pfm mode v in = 24v v in = 48v,60v v in = 12v v in = 36v 3.30 3.32 3.34 3.36 3.38 3.40 0 20 40 60 80 100 output voltage (v) load current (ma) output voltage vs. load current toc6 figure 7 application circuit, pfm mode v in = 48v v in = 12v, 24v v in = 36v v in = 60v 4.984 4.986 4.988 4.99 4.992 4.994 0 20 40 60 80 100 output voltage (v) load current (ma) output voltage vs. load current toc7 v in = 48v v in = 36v v in = 24v v in = 12v v in = 60v figure 6 application circuit, pwm mode 3.316 3.318 3.320 3.322 3.324 3.326 3.328 3.330 0 20 40 60 80 100 output voltage (v) load current (ma) output voltage vs. load current toc8 v in = 48v v in = 36v v in = 12v v in = 60v figure 7 application circuit, pwm mode v in = 24v 0.78 0.79 0.80 0.81 0.82 -40 -20 0 20 40 60 80 100 120 feedback voltage (v) temperature ( c ) feedback voltage vs. temperature toc9 maxim integrated 5 typical operating characteristics www.maximintegrated.com MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current
(v in = 24v, v gnd = 0v, v out = 3.3v, v en/uvlo = 1.5v, rt/sync = 191k, c in = 1f, t a = +25c unless otherwise noted) 0 20 40 60 80 100 5 15 25 35 45 55 no load supply current ( a) input voltage ( v ) no load supply current vs. input voltage toc10 pfm mode -2.0 -0.5 1.0 2.5 4.0 5 15 25 35 45 55 shutdown current ( a) input voltage ( v ) shutdown current vs. input voltage toc11 0.5 0.8 1.1 1.4 1.7 2.0 -40 -20 0 20 40 60 80 100 120 shutdown current ( a) temperature ( c ) shutdown current vs. temperature toc12 0 50 100 150 200 250 5 15 25 35 45 55 switch current limit (ma) input voltage (v) switch current limit vs. input voltage toc13 switch peak current limit switch negative current limit 0 50 100 150 200 250 -40 -20 0 20 40 60 80 100 120 switch current limit (ma) temperature ( c ) switch current limit vs. temperature toc14 switch peak current limit switch negative current limit 1.10 1.14 1.18 1.22 1.26 1.30 -40 -20 0 20 40 60 80 100 120 en/uvlo threshold voltage (v) temperature ( c ) en/uvlo threshold voltage vs. temperature toc15 rising falling 0 200 400 600 800 1000 -40 -20 0 20 40 60 80 100 120 switching frequency (kh z ) temperature ( c ) switching frequency vs. temperature toc16 r t = 191k ? r t = 69.8k ? r t = 45.3k ? r t = 422k ? 90 91 92 93 94 95 96 -40 -20 0 20 40 60 80 100 120 reset threshold (%) temperature ( c ) reset threshold vs. temperature toc17 rising falling 100mv/div 50ma/div toc18 200s/div v out (ac) i out load transient response, pfm mode (load current stepped from 5 m a to 50 m a) figure6 application circuit v out =5v figure 6 application circuit v out = 5v maxim integrated 6 7slfdo2sudwlqjkdudfwulvwlfvfqwlqx www.maximintegrated.com MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current
(v in = 24v, v gnd = 0v, v out = 3.3v, v en/uvlo = 1.5v, rt/sync = 191k, c in = 1f, t a = +25c unless otherwise noted) 100mv/div 50ma/div toc19 200s/div v out (ac) i out load transient response pfm mode (load current stepped from 5 m a to 50 m a) figure7 application circuit v out =3.3v figure 7 application circuit v out = 3.3v 100mv/div 50ma/div toc20 100s/div v out (ac) i out load transient response pfm or pwm mode (load current stepped from 50 m a to 100 m a) figure 6 application circuit v out = 5v 100mv/div 50ma/div toc21 100s/div v out (ac) i out load transient response pfm or pwm mode (load current stepped from 50 m a to 100 m a) figure 7 application circuit v out = 3.3v 100mv/div 50ma/div toc22 100s/div v out (ac) i out load transient response pwm mode (load current stepped from no load to 50 m a) figure 6 application circuit v out = 5v 100mv/ div toc23 100s/div v out (ac) i out load transient response pwm mode (load current stepped from no load to 50 m a) 50ma/div figure 7 application circuit v out = 3.3v 100mv/div toc24 10s/div v out (ac) i lx switching waveforms (pfm mode) 100ma/div lx 10mv/div figure 6 application circuit v out = 5v,load = 20ma 20mv/div toc25 4s/div v out (ac) i lx full load switching waveforms (pwm or pfm mode) 100ma/div lx 10v/div figure 6 application circuit v out = 5v, load = 100ma 20mv/div toc26 4s/div v out (ac) i lx no load switching waveforms (pwm mode) 100ma/div lx 10v/div figure 6 application circuit v out = 5v 2v/div 5v/div toc27 1ms/div v en/uvlo v out 50ma/div 5v/div soft - start i out v reset figure 6 application circuit v out = 5v maxim integrated 7 typical operating characteristics (continued) www.maximintegrated.com MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current
(v in = 24v, v gnd = 0v, v out = 3.3v, v en/uvlo = 1.5v, rt/sync = 191k, c in = 1f, t a = +25c unless otherwise noted) typical operating characteristics (continued) 1v/div 5v/div toc28 1ms/div v en/uvlo v out 50ma/div 5v/div soft - start i out v reset figure 7 application circuit v out = 3.3v 2v/div 5v/div toc29 1ms/div v en /uvlo v out 50ma/div 5v/div shutdown with enable i out v reset figure 6 application circuit v out = 5v 1v/div 5v/div toc30 1ms/div v en/uvlo v out 5v/div soft - start with 3v prebias v reset figure 6 application circuit no load, pwm mode 10v/div 100ma/div toc31 2s/div v rt/sync v lx 1v/div external synchronization i lx 100ma/div toc32 1ms/div v out 5v/div overload protection i lx toc33 bode plot figure 6 application circuit v out = 5v f cr = 8.5khz, phase margin = 64 gain phase toc34 bode plot figure 7 application circuit v out = 3.3v f cr = 10.5khz, phase margin = 61 gain phase maxim integrated 8 MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
MAX17552 top view 1 + 3 4 lx mode v out reset 2 gnd in rt/ sync ss en/ uvlo tdfn 3mm x 2mm 5 fb 10 8 7 9 6 10 2 3 4 5 9 8 7 6 gnd mode reset v out fb ss rt/sync en/uvlo max 3mm x 3mm + MAX17552 1 lx in pin name function switching regulator input. connect a x7r 1f ceramic capacitor from in to gnd for bypassing. active-high, enable/undervoltage-detection input. pull en/uvlo to gnd to disable the regulator en/uvlo, and gnd to program the input voltage at which the device is enabled and turns on. rt/sync oscillator timing resistor input. connect a resistor from rt/sync to gnd to program the switching frequency from 100khz to 2.2mhz. see the external pulse can be applied to rt/sync through a coupling capacitor to synchronize the internal clock soft-start capacitor input. connect a capacitor from ss to gnd to set the soft-start time. leave ss and gnd to set the external bias input for internal control circuitry. decouple to gnd with a 0.22f capacitor and connect to output capacitor positive terminal with a 22.1 resistor for applications with an output voltage from 3.3v to 5v. connect to gnd for output voltages < 3.3v and > 5v. see the reset open-drain reset output. pull up pfm/pwm mode-selection input. connect mode to gnd to enable the fxed-frequency pwm gnd ground. connect gnd to the power ground plane. connect all the circuit ground connections together at exposed pad (tdfn only). connect to the gnd pin to the ic. pin description pin confguration MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
en/uvlo 1.25v i n t er n al ldo regulator pf m/pwm control logic 1.22v mo d e t h e rma l shutdown mo d e sel ec t c h i pen f b pw m c s sl o pe internal or external soft-start control error amplifier o sci l l a t o r c l k sl o pe peak-limit pf m h i g h -si d e driver current- sense logic low-si d e driver d h d l si n k-limit c s lx r eset g n d ss r t/sync vc c_int i n v o u t vc c_int po k c l k c u r r e n t- sense amplifier c u r r e n t sense amplifier 2ms delay 0.76v negative current ref fb MAX17552 maxim integrated 10 block diagram MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
detailed description the MAX17552 high-efficiency, high-voltage, syn - chronous step-down dc-dc converter with integrated mosfets operates over a 4v to 60v input voltage range. the converter can deliver output current up to 100ma at output voltages of 0.8v to 0.9 x v in . the output voltage is accurate to within 1.75% over -40c to +125c. the converter consumes only 22a of supply current in pfm mode while regulating the output voltage at no load. the device uses an internally compensated, peak- current-mode control architecture ( see the block diagram ). on the rising edge of the internal clock, the high-side p-mosfet turns on. an internal error amplifier compares the feedback voltage to a fixed internal refer - ence voltage and generates an error voltage. the error voltage is compared to a sum of the current-sense voltage and a slope-compensation voltage by a pwm comparator to set the on-time. during the on-time of the pmosfet, the inductor current ramps up. for the remainder of the switching period (off-time), the pmosfet is kept off and the low-side nmosfet turns on. during the off-time, the inductor releases the stored energy as the inductor current ramps down, providing current to the output. under overload conditions, cycle-by-cycle current-limit feature limits inductor peak current by turning off the high- side pmosfet and turning on the low-side nmosfet. mode selection (mode) the device features a mode pin for selecting either forced-pwm or pfm mode of operation. if the mode pin is left unconnected, the device operates in pfm mode at light loads. if the mode pin is grounded, the device operates in a constant-frequency forced-pwm mode at all loads. mode of operation can be changed on-the-fly during normal operation of the device. in pwm mode, the inductor current is allowed to go negative. pwm operation is useful in frequency-sensitive applications and provides fixed switching frequency at all loads. however, the pwm mode of operation gives lower efficiency at light loads compared to pfm mode of operation. pfm mode disables negative inductor current and addi - tionally skips pulses at light loads for high efficiency. in pfm mode, the inductor current is forced to a fixed peak of 72ma (typ) (i pfm ) every clock cycle until the output rises to 102% (typ) of the nominal voltage. once the output reaches 102% (typ) of the nominal voltage, both high-side and low-side fets are turned off and the device enters hibernate operation until the load discharges the output to 101% (typ) of the nominal voltage. most of the internal blocks are turned off in hibernate operation to save quiescent current. after the output falls below 101% (typ) of the nominal voltage, the device comes out of hibernate operation, turns on all internal blocks, and again commences the process of delivering pulses of energy to the output until it reaches 102% (typ) of the nominal output voltage. the device naturally exits pfm mode when the load current increases to a magnitude of approximately: i pfm - (i/2) where i is the peak-peak ripple current in the output inductor. the part enters pfm mode again if the load current reduces to approximately (i/2). see the inductor selection section for details. the advantage of the pfm mode is higher efficiency at light loads because of lower current drawn from the supply. enable input (en/uvlo) and soft-start (ss) when en/uvlo voltage increases above 1.25v (typ), the device initiates a soft-start sequence and the duration of the soft-start depends on the status of the ss pin voltage at the time of power-up. if the ss pin is not connected, the device uses a fixed 5ms internal soft-start to ramp up the internal error-amplifier reference. if a capacitor is connected from ss to gnd, a 5a current source charges the capacitor and ramps up the ss pin voltage. the ss pin voltage is used as reference for the internal error amplifier. such a reference ramp up allows the output voltage to increase monotonically from zero to the final set value independent of the load current. en/uvlo can be used as an input voltage uvlo- adjustment input. an external voltage-divider between in and en/uvlo to gnd adjusts the input voltage at which the device turns on or turns off. see the setting the input undervoltage-lockout level section for details. if input uvlo programming is not desired, connect en/ uvlo to in (see the electrical characteristics table for en/uvlo rising and falling-threshold voltages). driving en/uvlo low disables both power mosfets, as well as other internal circuitry, and reduces in quiescent current to below 1.2 a. the ss capacitor is discharged with an internal pulldown resistor when en/uvlo is low. if the en/uvlo pin is driven from an external signal source, a series resistance of minimum 1k w is recommended to be placed between the signal source output and the en/ uvlo pin, to reduce voltage ringing on the line. maxim integrated 11 MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
switching frequency (rt/sync) switching frequency of the device can be programmed from 100khz to 2.2mhz by using a resistor connected from rt/sync to gnd. the switching frequency (f sw ) is related to the resistor connected at the rt/sync pin (r t ) by the following equation, where r t is in k and f sw is in khz: t sw 42000 r f = the switching frequency in ranges of 130khz to 160khz and 230khz to 280khz are not allowed for user pro - gramming to ensure proper configuration of the internal adaptive-loop compensation scheme. external synchronization the rt/sync pin can be used to synchronize the devices internal oscillator to an external system clock. the external clock should be coupled to the rt/sync pin through a 47pf capacitor, as shown in figure 1 . the external clock logic high level should be higher than 3v, logic low level lower than 0.5v and the duty cycle of the external clock should be in the range of 10% to 70%. external clock synchronization is allowed only in pwm mode of operation (mode pin connected to gnd). the rt resistor should be selected to set the switching fre - quency 10% lower than the external clock frequency. the external clock should be applied at least 500s after enabling the device, for proper configuration of the inter - nal loop compensation. external bias (v out ) the device provides a v out pin to power the internal blocks from a low-voltage supply. when the v out pin voltage exceeds 3.1v, the device draws switching and quiescent current from this pin to improve the converters efficiency. in applications with an output voltage setting from 3.3v to 5v, v out should be decoupled to gnd with a ceramic capacitor, and should be connected to the positive terminal of the output capacitor with a resistor (r4, c1) as shown in the typical application circuits. in the absence of r4 and c1, the absolute maximum rat - ing of v out (-0.3v) can be exceeded under short-circuit conditions, due to oscillations between the ceramic output capacitor and the inductance of the short-circuit path. in general, parasitic board or wiring inductance should be minimized and the output voltage waveform under short circuit operation should be verified to ensure that the absolute maximum rating of v out is not exceeded. for applications with an output voltage setting less than 3.3v or greater than 5v, v out should be connected to gnd. reset output ( reset ) the device includes an open-drain reset output to monitor output voltage. reset should be pulled up with an external resistor to the desired external power supply. reset goes high impedance 2ms after the output rises above 95% of its nominal set value and pulls low when the output voltage falls below 92% of the set nominal output voltage. startup into a prebiased output the device supports monotonic startup into a prebiased output. when the device starts into a prebiased output, both the high-side and low-side switches are turned off so that the converter does not sink current from the output. high-side and low-side switches do not start switching until the pwm comparator commands the first pwm pulse, at which point switching commences. the output voltage is then smoothly ramped up to the target value in alignment with the internal reference. such a feature is useful in applications where digital integrated circuits with multiple rails are powered. operating input voltage range the maximum operating input voltage is determined by the minimum controllable on-time, and the minimum operating input voltage is determined by the maximum figure 1. synchronization to an external clock clock source duty 47pf r t rt/sync v logic-low MAX17552 v logic-high maxim integrated 12 MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
duty cycle and circuit voltage drops. the minimum and maximum operating input voltages for a given output volt - age should be calculated as follows: out out dcr inmin out max v (i (r 2.6)) v (i 2.5) d + + = + out inmax onmin sw v v tf = where v out is the steady-state output voltage, i out is the maximum load current, r dcr is the dc resistance of the inductor, f sw is the switching frequency (max), d max is the maximum duty cycle (0.9), and t onmin is the worst- case minimum controllable switch on-time (128ns) overcurrent protection the device implements a hysteretic cycle-by-cycle peak- current limit protection scheme to protect the inductor and internal fets under output short circuit conditions. when the inductor peak current exceeds 0.21a (typ), high side switch is turned off and low side switch is turned on to dis - charge the inductor current. subsequent clock pulses do not turn on the high-side switch until inductor current dis - charges to 0.15a (typ). this operation continues until over - load/short circuit is removed on the output. since the induc - tor current is bounded between two limits, inductor current runaway never happens in this scheme. additionally, hysteretic negative peak current limit controls the low-side switch negative current when it exceeds 0.1a (typ). thermal-overload protection thermal-overload protection limits the total power dissi - pation in the ic. when the junction temperature exceeds +160c, an on-chip thermal sensor shuts down the device, turns off the internal power mosfets, allowing the device to cool down. the device turns on after the junction temperature cools by 20c. applications information inductor selection a low-loss inductor having the lowest possible dc resis - tance that fits in the allotted dimensions should be select - ed. calculate the required inductance from the equation: where l is inductance in h, v out is output voltage and f sw is the switching frequency in khz. calculate the peak-peak ripple current (i) in the output inductor from the equation: out out in sw v 1000 v 1 v i fl ? ?? ?? ?? ?= where l is inductance in h, v out is output voltage, v in is input voltage and f sw is the switching frequency in khz. the saturation current rating of the inductor must exceed the maximum current-limit value (i peak-limit ). the satu - ration current rating should be the maximum of either 0.235a or the value from the equation: inmax on min sat vt i 0.15 l ? = + where l is inductance in h, v inmax is maximum input voltage and t on-min is worst case minimum on time (128ns). once the l value is known, the next step is to select the right core material. ferrite and powdered iron are com - monly available core materials. ferrite cores have low core losses and are preferred for high-efficiency designs. powdered iron cores have more core losses and are rela - tively cheaper than ferrite cores. input capacitor selection small ceramic input capacitors are recommended for the ic. the input capacitor reduces peak current drawn from the power source and reduces noise and voltage ripple on the input caused by the switching circuitry. a minimum of 1f, x7r-grade capacitor in a package larger than 0805 is recommended for the input capacitor of the ic to keep the input-voltage ripple under 2% of the minimum input voltage, and to meet the maximum ripple-current requirements. output capacitor selection small ceramic x7r-grade output capacitors are recom - mended for the device. the output capacitor has two functions. it stores sufficient energy to support the output voltage under load transient conditions and stabilizes the devices internal control loop. usually the output capacitor is sized to support a step load of 50% of the maximum output current in the application, such that the output- voltage deviation is less than 3%. calculate the minimum required output capacitance from the following equations: out sw 10000 x v l = f maxim integrated 13 MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
it should be noted that dielectric materials used in ceramic capacitors exhibit capacitance loss due to dc bias lev - els and should be appropriately derated to ensure the required output capacitance is obtained in the application. soft-start capacitor selection the device offers a 5.1ms internal soft-start when the ss pin is left unconnected. when adjustable soft-start time is required, connect a capacitor from ss to gnd to program the soft-start time. soft-start time (t ss ) is related to the capacitor connected at ss (c ss ) by the following equation: ss ss c 6.25 t = where t ss is in milliseconds and c ss is in nanofarads. setting the input undervoltage-lockout level the device offers an adjustable input undervoltage- lockout level. set the voltage at which the device turns on with a resistive voltage-divider connected from in to gnd (see figure 2 ). connect the center node of the divider to en/uvlo. choose r1 to be 3.3m max and then calculate r2 as follows: inu r1 1.25 r2 (v - 1.25) = where v inu is the voltage at which the device is required to turn on. adjusting the output voltage the output voltage can be programmed from 0.8v to 0.9 x v in . set the output voltage by connecting a resistor- divider from output to fb to gnd (see figure 3 ). choose r2 in the range of 25k to 100k and calculate r1 with the following equation: out v r1 r2 1 0.8 ? ?? = ?? ?? transient protection in applications where fast line transients or oscillations with a slew rate in exces of 15v/s are expected dur - ing power-up or steady-state operation, the MAX17552 should be protected with a series resistor that forms a lowpass filter with the input ceramic capacitor ( figure 4 ). these transients can occur in conditions such as hot- plugging from a low-impedance source or due to inductive load switching and surges on the supply lines. frequency range (khz) minimum output capacitance (f) 100 to 130 out 50 v 160 to 230 out 25 v 280 to 2200 out 17 v figure 2. adjustable en/uvlo network figure 3. setting the output voltage r2 en/uvlo in MAX17552 r1 v in r2 fb MAX17552 r1 v out gnd maxim integrated 14 MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
power dissipation ensure that the junction temperature of the device does not exceed 125c under the operating conditions speci - fied for the power supply. at a particular operating condi - tion, the power losses that lead to temperature rise of the device are estimated as follows: 2 loss out out dcr 1 p p - 1 - (i r ) ?? ?? = ?? ?? ?? ?? out out out p vi = where p out is the output power, is the efficiency of power conversion, and r dcr is the dc resistance of the output inductor. see the typical operating characteristics for the power-conversion efficiency or measure the effi - ciency to determine the total power dissipation. the junction temperature (t j ) of the device can be estimated at any ambient temperature (t a ) from the following equation: ( ) j a ja loss tt p = + where ja is the junction-to-ambient thermal impedance of the package. pcb layout guidelines careful pcb layout ( figure 5 ) is critical to achieve clean and stable operation. the switching power stage requires particular attention. follow these guidelines for good pcb layout: place the input ceramic capacitor as close as possible to v in and gnd pins minimize the area formed by the lx pin and inductor connection to reduce the radiated emi ensure that all feedback connections are short and direct route high-speed switching node (lx) away from the signal pins for a sample pcb layout that ensures the first-pass success, refer to the MAX17552 evaluation kit data sheet. figure 4. transient protection 4.7 in MAX17552 gnd c in 1 f maxim integrated 15 MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
figure 5. layout guidelines l x r eset g n d i n en/uvlo ss mo d e l1 c out f b r t/sync v o u t v o u t r4 r5 v out v in MAX17552 c in r3 r6 r2 r1 c ss c in c out v in plane g n d plane r5 r4 r6 r2 u1 l1 r3 r1 vias to bottom side g round plane vias to v out c ss g n d plane i n e n / u v l o r t / s y n c s s f b v o u t r e s e t m o d e g n d l x v out plane c f r7 c f r7 maxim integrated 16 MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
figure 6. high-efficiency 5v, 100ma regulator figure 7. high-efficiency 3.3v, 100ma regulator figure 8. small footprint 5v, 100ma regulator l1 coilcraft lps5030-224m c out murata 10 f/x7r/6.3v/1206 (grm31cr70j106k) c in murata 1 f/x7r/100v/1206 (grm31cr72a105k) l x r eset g n d i n en/uvlo ss mo d e l1 220 h f b r t/sync v o u t r1 261k ? r2 49.9k ? v out 5v, 100ma v in 6v to 60v c in 1 f c out 10 f r3 191k ? MAX17552 r4 22.1 ? c1 0.22 f l1 coilcraft lps5030-154m c out murata 10 f/x7r/6.3v/1206 (grm31cr70j106k) c in murata 1 f/x7r/100v/1206 (grm31cr72a105k) l x r eset g n d i n en/uvlo ss mo d e l1 150 h f b r t/sync v o u t r1 158k ? r2 49.9k ? v out 3.3v, 100ma v in 4v to 60v c in 1 f c out 10 f r3 191k ? MAX17552 r4 22.1 ? c1 0.22 f l1 coilcraft lps3015-104m c out murata 10 f/x7r/6.3v/0805 (grm21br70j106k) c in murata 1 f/x7r/100v/1206 (grm31cr72a105k) l x r eset g n d i n en/uvlo ss mo d e l1 100 h f b r t/sync v o u t r1 261k ? r2 49.9k ? v out 5v, 100ma v in 6v to 60v c in 1 f c out 10 f r3 69.8k ? MAX17552 r4 22.1 ? c1 0.22 f maxim integrated typical application circuits MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
figure 10. small footprint 1.8v, 100ma regulator figure 9. small footprint 3.3v, 100ma regulator figure 11. small footprint 12v, 100ma step-down regulator l1 coilcraft lps3015-683m c out murata 10 f/x7r/6.3v/0805 (grm21br70j106k) c in murata 1 f/x7r/100v/1206 (grm31cr72a105k) l x r eset g n d i n en/uvlo ss mo d e l1 68 h f b r t/sync v o u t r1 158k ? r2 49.9k ? v out 3.3v, 100ma v in 4v to 45v c in 1 f c out 10 f r3 69.8k ? MAX17552 r4 22.1 ? c1 0.22 f l1 coilcraft lps3015-333m c out murata 10 f/x7r/6.3v/1206 (grm31cr70j106k) c in murata 1 f/x7r/100v/1206 (grm31cr72a105k) l x r eset g n d i n en/uvlo ss mo d e l1 33 h f b r t/sync v o u t r1 127k ? r2 100k ? v out 1.8v, 100ma v in 4v to 24v c in 1 f c out 10 f r3 69.8k ? MAX17552 l1 coilcraft lps5030-224m c out murata 10 f/x7r/16v/1206 (grm31cr71c106k) c in murata 1 f/x7r/100v/1206 (grm31cr72a105k) l x r eset g n d i n en/uvlo ss mo d e l1 2 2 0 h f b r t/sync v o u t r1 348k ? r2 24.9k ? v out 12v, 100ma v in 15v to 60v c in 1 f c out 10 f r3 69.8k ? MAX17552 maxim integrated typical application circuits (continued) MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
+denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. part temp range pin-package MAX17552atb+ -40c to +125c 10 tdfn-ep* MAX17552aub+ -40c to +125c 10 max package type package code outline no. land pattern no. 10 tdfn-ep t1032n+1 21-0429 90-0082 10 max u10+5 21-0061 90-0330 maxim integrated 19 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos ordering information MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current www.maximintegrated.com
revision number revision date description pages changed 0 2/14 initial release 1 6/14 added statement regarding en/uvlo connection 11 ? 2014 maxim integrated products, inc. 20 revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX17552 60v, 100ma, ultra-small, high-effciency synchronous step-down dc-dc converter with 22a no-load supply current for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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